Engineered for seamless system integration, our Module PCBs feature precision Half-Via (Castellated Hole) technology with a $\pm 0.05\text{mm}$ tolerance. Optimized for IoT and RF applications, our manufacturing process ensures burr-free edges and $\pm 5\%$ impedance control to maintain signal integrity across ultra-thin substrates. From ISO Class 5 cleanrooms to IATF 16949-certified mass production, we deliver the reliability required for high-yield SMT assembly.
1. Technical Overview
In modular hardware design, the Module PCB functions as a surface-mounted sub-assembly that requires precise mechanical and electrical interfacing. Our manufacturing process focuses on the structural integrity of Castellated Holes (Half-Vias) and the consistency of high-frequency signal paths. By utilizing controlled secondary routing and mSAP-compatible workflows, we ensure that modules are optimized for high-yield automated SMT assembly.
2. Manufacturing Specifications
Technical Category
Engineering Standard
Advanced Capability
Min Half-Via Diameter
$0.50\text{ mm}$
$0.40\text{ mm}$
Half-Via Tolerance
$\pm 0.05\text{ mm}$
$\pm 0.03\text{ mm}$
Min Pitch (Center-to-Center)
$1.27\text{ mm}$
$1.00\text{ mm}$
Surface Finish
ENIG / OSP
ENEPIG / Immersion Silver
Impedance Tolerance
$\pm 10\%$
$\pm 5\%$
Copper Weight (Barrel)
$\ge 20\mu\text{m}$
Customizable
3. Process Details & Visual Verification
Caption: High-resolution inspection of burr-free half-vias post-singulation.
Caption: Micro-section analysis verifying plating thickness and interfacial integrity.
4. Design Guidelines for Engineering
To maintain reliability across production lots, the following design parameters are recommended:
Annular Ring Requirements: Outer layer pads should be a minimum of $0.15\text{ mm}$ larger than the drill radius to prevent annular ring breakout during routing.
Trace Clearance: Traces and vias (excluding the castellations) must maintain a $0.25\text{ mm}$ setback from the edge to avoid mechanical delamination.
Tie-Bar Management: Internal copper planes should be pulled back from the cutting line to prevent potential shorts during the singulation phase.
Material Selection: For RF modules, low-loss laminates (e.g., Rogers or high-Tg FR4) are utilized to maintain signal integrity at the half-via transition point.
5. Technical FAQ
Q: How is the "burr-free" edge achieved in mass production?
A: We utilize a two-stage fabrication sequence: initial plating followed by a precision-controlled secondary routing stage using customized CNC parameters. This prevents the copper from tearing away from the substrate.
Q: What surface finish is optimal for modules stored for long periods?
A:ENEPIG is recommended. The palladium layer provides a superior barrier against oxidation on the exposed edges of the half-vias, ensuring solderability remains within spec for $12+$ months.
Q: Are 100% impedance tests conducted on module boards?
A: Yes. We perform TDR (Time Domain Reflectometry) testing on dedicated coupons or in-circuit traces upon request to verify compliance with $50\Omega$ or $100\Omega$ requirements.
6. Submission Requirements for RFQ
For technical review and quotation, please provide the following documentation:
Gerber Data: RS-274X or ODB++ format.
Stack-up: Detailed layer buildup and dielectric requirements.
Finish Spec: Specified surface treatment and copper weights.
