PCB/PCBA RFQ-Vorlage: Was Sie für ein schnelles, genaues Angebot einbeziehen sollten
A complete RFQ helps engineering, CAM, and purchasing align quickly—reducing back-and-forth and avoiding surprises on cost, lead time, and yield. Use the checklist and copy-paste templates below to get a firm quote fast.
1) Company & Project Basics
- Company & site: legal entity, billing & ship-to addresses
- Project name / part no.: e.g., RFGW-Main-Board-A
- NDA/IP: attach your NDA or request ours (mutual NDA available)
- Contact windows: technical owner + commercial owner, email/phone
- Build purpose: prototype / pilot run / mass production; target SOP date
- Incoterms & destination: e.g., DAP Munich, Germany / EXW Shenzhen, China
2) PCB Fabrication Data (Design Package)
Accepted formats: Gerber RS-274X (with drill files), ODB++, IPC-2581
Include: Readme.txt (file list & notes), fabrication drawing, panel drawing (if any)
PCB Spec Table (fill the blanks):
| Artikel | Requirement |
|---|---|
| Layer count | __ (e.g., 6L / 10L HDI L1-L2 & L9-L10 microvias) |
| Board size / outline | __ mm × __ mm; outline in mechanical layer |
| Finished thickness | __ mm (± __ mm) |
| Material | FR-4 High-TG / Low-loss (Dk/Df) / Hybrid; Tg ≥ __ °C |
| Copper weight | Outer: __ oz; Inner: __ oz |
| Min trace/space | __ / __ mil (≥ 3/3 mil preferred unless approved) |
| Min drill | Laser uVia __ mil; Mech via __ mm; via type: blind/buried/VIP |
| Via-in-Pad | Yes/No; fill type (resin / copper); cap requirement |
| Oberflächengüte | ENIG / ENEPIG / Imm Ag / OSP (specify thickness if needed) |
| Soldermask & legend | Color, gloss, min clearance, plugged vias (Y/N) |
| Impedanz | 50 Ω SE, 90/100 Ω diff (list all targets) |
| Tolerance | ±__% (default ±10% unless otherwise agreed) |
| Flatness/warpage | ≤ __% or ≤ __ mm per __ mm |
| Cleanliness | Ionic contamination limit if required; no-clean compatibility |
| UL/Flammability | UL mark (Y/N); CTI; FR rating |
| Acceptance | IPC-6012 Class __; soldermask per IPC-SM-840 Class __ |
| Tests | E-test 100% (default), impedance coupon per panel, others… |
| Special | Back-drill (layers __ to __), controlled depth routing, castellations |
Optional: Impedance/Stackup Attachment
- Proposed stackup table (core/prepreg thickness, glass style, copper foil), targets per layer pair, and which nets are critical.
File naming (recommendation):Project_PCB_FAB_v1.2_YYYYMMDD.zip with subfolders /Gerber, /Drills, /Drawings, /Readme.
3) PCBA (Assembly) Data
Accepted formats: BOM (XLSX/CSV), Centroid/Pick-&-Place (CSV/TXT), Assembly drawing, 3D (STEP), XY data per side, test spec (if any).
BOM Essentials:
- Line item, Qty/board, Manufacturer, MPN, Description, Package, Voltage/Power notes
- Substitutions: allowed Y/N; if Y, define “Form-Fit-Function” rules (e.g., same footprint & equal/higher specs)
- Customer-supplied parts (consigned): list with incoming qty and reels/trays
Sample BOM Row Format:
| Line | Designator(s) | Qty/PCB | Mfr | MPN | Package | Notes |
|---|---|---|---|---|---|---|
| 10 | U3 | 1 | TI | TPS5430DDAR | SO-PowerPAD | Alt OK: same pinout, ≥3A |
| 20 | C1,C5,C12 | 3 | Murata | GRM21BR61C106KE15 | 0805 | 10µF, 16V, X5R |
Assembly Spec Table:
| Artikel | Requirement |
|---|---|
| Sides | Top only / Top & Bottom |
| Technology | SMT / THD / mixed; BGA µBGA pitch (e.g., 0.5 mm) |
| Solder type | Lead-free SAC305 / SnPb; paste type & alloy if specified |
| Stencil | Vendor to make / customer provided; thickness __ mm; aperture reductions |
| Reflow profile | Provide guidance if special; max component temp limits |
| Cleaning | No-clean / aqueous / required ionic level |
| Underfill/adhesives | Yes/No; material spec |
| Conformal coat | Yes/No; material (e.g., HumiSeal 1B31); masked areas |
| Potting | Yes/No; resin type & keep-outs |
| Labels & traceability | SN format, QR/1D code location, logo or UL marks |
| Acceptance | IPC-A-610 Class __; BGA X-ray coverage (%) |
4) Test & Programming
- Electrical test: flying-probe / ICT / boundary scan / functional test
- Test coverage (goal): e.g., ≥ 85% nets via ICT + boundary scan
- Fixtures: who owns cost; reusable across revisions (Y/N)
- FW programming: toolchain, HEX/ELF, programming header, serial rules
- Pass/Fail limits & logs: what data to deliver (CSV, screenshots, trace files)
Minimal Test Spec Example:
| Artikel | Spec |
|---|---|
| Power-on | < 100 mA at 12 V idle |
| Clock | 25 MHz within ±50 ppm |
| Interfaces | UART loopback, I²C scan, Ethernet link up |
| Calibration | ADC offset ±2 LSB; store in EEPROM |
| Report | Serial + timestamp + pass/fail to CSV |
5) Packaging & Logistics
- ESD packing: board/assembly level (ESD bags, desiccant, HIC, vacuum)
- Panelization: vendor to panelize (Y/N); rails/fiducials/break-off style
- Labeling: PN, Rev, Lot, Qty, RoHS, country-of-origin
- Shipping: courier preference, insurance, temperature control (if needed)
6) Quality, Documentation & Change Control
- Certificates: RoHS/REACH declaration, COC/COA, material certs if required
- Sampling / AQL: default IPC sampling or specify AQL levels (e.g., 0.65/1.0)
- Deviations: process for pre-approved deviations (DCR/ECO form)
- FAI/PPAP (if automotive): level, submission items, gauge R&R ownership
- Data retention: how long to keep build records, stencil/fixtures, test logs
7) Lead Time & Build Plan (fill what you need)
- PCB only: proto __ working days; repeat __ days
- PCBA (turn-key): proto __ days after materials in; pilot __ days; MP __ days
- Split quote: PCB-only / consigned-kit / full turn-key
- Price breaks: 5/10/50/100/500 pcs
- SLA: OTD target __%; expedite options (Y/N)
8) Cost Drivers to Call Out Early
- Ultra-fine line/space (< 3/3 mil), stacked uVias, via-in-pad with fill & cap
- Low-loss or hybrid materials, back-drill, heavy copper on inner layers
- BGA ≤ 0.4 mm pitch, tight coplanarity, conformal coat / potting
- ICT fixtures, functional test development, programming at line speed
- Special cleanliness, ionics, or reliability testing
9) Copy-Paste RFQ Email (PCB-Only)
Subject: RFQ – 6-Layer HDI PCB – Project RFGW-Main-Board-A – DAP Munich
Body:
Dear BenChuang Team,
Please quote the attached PCB per the following:
- Qty/Delivery: 20 pcs proto (10 WD), 200 pcs (15 WD), 1,000 pcs (20 WD)
- Material: FR-4 High-TG ≥170°C; Finished thickness 1.6 mm
- Layers: 6L with L1-L2 and L5-L6 microvias, staggered
- Min line/space: 3/3 mil; Min vias: laser 4 mil, mechanical 0.2 mm
- Surface finish: ENIG; Soldermask: Green; Legend: White
- Impedance: 50 Ω SE; 100 Ω diff on L3-L4 (±10%); coupon per panel
- Tests: 100% E-test; cross-section on first lot
- Acceptance: IPC-6012 Class 2
- Deliverables: COC, impedance/TDR report, dimensional report
Attached: Gerber+Drill, Fab drawing, Stackup proposal, Readme.txt
Incoterms: DAP Munich, Germany
Please quote PCB-only and add expedite option if available.
Regards,
<Name, Title>
<Company, Address>
<Tel, Email>
10) Copy-Paste RFQ Email (Turn-Key PCBA)
Subject: RFQ – Turn-Key PCBA – 10L HDI – Project ADAS-Controller-B – EXW Shenzhen
Body:
Dear BenChuang Team,
We request a turn-key PCBA quote:
- Qty/Delivery: 30 pcs proto (12 WD ARO), 300 pcs pilot (20 WD), 2,000 pcs MP (25 WD)
- PCB: 10L HDI, 1.6 mm, ENIG, 3/3 mil, VIP under 0.5 mm BGA
- Assembly: SMT both sides + selective THD; SAC305; no-clean
- Test: FCT with UART, I2C, Ethernet; BGA X-ray 100%
- Programming: SW v1.4, HEX provided; unique serial QR; log to CSV
- Labels: PN, Rev, Lot, SN; CoO China
- Acceptance: IPC-A-610 Class 2
Attached: BOM (xlsx with MPNs), PnP (CSV), Gerber/ODB++, STEP, Assembly drawings, Test spec, Label spec.
Please quote:
1) PCB only
2) PCBA with consigned passives
3) Full turn-key (all materials)
Include stencil/fixture cost and lead time breakdown.
Regards,
<Name, Title>
<Company, Address>
<Tel, Email>
11) One-Page RFQ Form Fields (for your website)
Use these fields on your “Get a Quote” page to capture everything in one go:
Project & Files
- Project/Part No.
- Upload: Gerber/ODB++/IPC-2581, BOM, PnP, STEP, Drawings
- NDA: attach / request mutual NDA
PCB
- Layers | Size | Thickness | Material | Cu weight (outer/inner)
- Min line/space | Min via (laser/mech) | Via-in-Pad (Y/N, fill)
- Surface finish | Mask/Legend | Impedance targets | Back-drill (Y/N)
Montage
- Sides | Solder alloy | Stencil (vendor/customer)
- Special: underfill, conformal coat, potting
- Test & programming (attach spec)
Commercial
- Qty breaks | Target lead time | Incoterms & destination
- Substitution policy (Y/N; rules) | Price-vs-lead preference
- Certificates needed (RoHS/REACH/UL/PPAP/FAI)
Contact
- Tech owner | Purchasing owner | Phone/Email
12) Common Pitfalls (and How to Avoid Them)
- No stackup or impedance targets: include a simple table or let us propose one.
- Missing centroid or mismatched ref-des: export PnP from the same CAD revision as the BOM.
- Unclear substitutions: specify “no substitutions” for critical ICs; allow parametric passives.
- Panel left undefined: if you need specific rails/break-offs, attach a panel drawing.
- Testing left for later: even a minimal pass/fail list avoids delays.
Final Note
If you send complete fabrication + assembly data, target impedance, and test coverage expectations, you’ll receive a firm quote faster, with fewer ECOs later. If you like, I can convert this into a downloadable RFQ PDF und eine web form field map for your site—just say the word and share any house rules you already use.
